Integrated imaging circuits are widely used to produce video and photographic images in digital cameras, copiers, scanners and other devices. Most integrated imaging circuits employ an array of photoactive pixels arranged in rows and columns for capturing images projected on the array. The pixels typically include photoactive or photoreceptive devices, such as photodiodes, in addition to adjacent transistor structures, such as transfer gate structures and reset transistors. Incident light that impacts an image sensor cell discharges the photodiode such that the resulting voltage drop can be used to determine the intensity level of the incident light. The transistors, as well as additional devices used for control and signal circuits in the peripheral regions of the image sensor cell, include complementary metal oxide semiconductor (CMOS) devices.
Shallow trench isolation (STI) is a known technique used to isolate pixels, devices or circuitry from one another in an imaging device. A trench is etched into a substrate and filled with a dielectric material, such as silicon dioxide (SiO2), to provide a physical and electrical barrier between adjacent pixels, devices, or circuitry. FIG. 1 illustrates a photodiode 100 with shallow trench isolations (STIs) 132 within the substrate 101. The photodiode 100 also includes p-well regions 126, an n-well region 128 and conductive gates 125. The STIs 132 have a depth of about 0.2 μm. Incident light travels into an interface between the p-well and the n-well (the p-n junction). When the p-n junction diode is reverse biased by application of a voltage to the p-n junction, a depletion region 129 forms as electrons diffuse from the n-well region 128 to the p-well regions 126. As a result, electron hole pairs are generated both inside and outside the depletion region 129. The photo-generated electron hole pairs diffuse and drift into the depletion region 129, inducing a photo current representing a portion of the image to which the photodiode was exposed.
During the STI process, a number of lattice defects, such as dangling bonds and stress-induced defects, may be introduced at vertical surfaces 130 in the substrate 101. Such defects may lead to the accumulation of electron hole pairs at the interface between the substrate 101 and the vertical surfaces 130 within the substrate 101. As voltage is applied, the depletion region 129 extends toward the vertical surfaces 130 in the substrate 101 in the vicinity of the oxide material of the STI, resulting in the accumulation of electron hole pairs at the interface of the STI 132 and depletion region 129. Accumulation of electron hole pairs resulting from damaged vertical surfaces 130 in the substrate 101 may have detrimental effects on the function of the photodiode. Such effects include an increased level of reverse bias leakage or dark current in the photodiodes. As used herein, the term “dark current” means and includes the leakage current discharged from a photodiode even when there is no incident light upon the image sensing element. Dark current arises from stress-related dislocations, such as dangling bonds, formed in the area around the interface between STIs 132 and the depletion region 129.
U.S. Pat. No. 7,187,023 to Yoshihara describes a solid-state imaging device having a first element isolation layer in a pixel array region of a semiconductor substrate and a second element isolation layer in a peripheral device region of the semiconductor substrate. The first element isolation layer is located partially within the semiconductor substrate and extends above the surface of the semiconductor substrate. The second element isolation layer is an STI and a portion thereof is formed within the semiconductor substrate and a portion thereof protrudes above the surface of the semiconductor substrate.
Wile imager devices fabricated using STI processes have achieved a relatively high level of commercial success, such imager devices exhibit some undesirable structural characteristics and operational deficiencies. Thus, there is a need in the art for imager device designs and fabrication processes resulting in imager devices having increased efficiency, reliability and durability.